1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device which can reduce an etching damage caused by removal of a resist.
2. Description of the Background Art
When a size of an MOSFET (Metal Oxide Silicon Field Effect Transistor) is reduced, a channel resistance is dropped. In order to obtain a transistor having a high driving capability, therefore, a parasitic resistance should be reduced as much as possible. A step of removing a resist to be used for a photolithographic process offers a problem.
While the resist is removed by etching, a semiconductor substrate is also etched slightly. In recent years, an MOSFET having a gate length of approximately 0.1 xcexcm has been developed through a reduction in a size. In such an MOSFET, however, a depth of a source-drain layer is also reduced. Thus, the slight etching of the semiconductor substrate cannot be disregarded.
In particular, an N-channel MOSFET (which will be hereinafter referred to as an NMOS transistor) has a lower channel resistance than that of a P-channel MOSFET (which will be hereinafter referred to as a PMOS transistor). Therefore, when the depth of the source-drain layer is further reduced due to the etching of the semiconductor substrate so that the parasitic resistance is slightly increased, an operating characteristic of the transistor is affected, which is not negligible.
In a conventional art, however, the etching of the semiconductor substrate caused by the removal of the resist has not been particularly recognized as a problem. For example, in a CMOS (Complementary MOS) transistor using a combination of the NMOS transistor and the PMOS transistor, the NMOS transistor and the PMOS transistor are formed adjacently to each other. However, the NMOS transistor has not been considered especially.
A conventional method of manufacturing a CMOS transistor will be described below with reference to FIGS. 42 to 49.
At a step shown in FIG. 42, first of all, an element isolating film 2 is selectively formed in a surface of a silicon substrate 1 to define an NMOS region NR and a PMOS region PR which form an NMOS transistor and a PMOS transistor, respectively. Then, an N well region NW containing an N-type impurity and a P well region PW containing a P-type impurity are formed in the surface of the silicon substrate 1 corresponding to the NMOS region NR and the PMOS region PR, respectively. Thereafter, a gate insulating film 3 is formed on the silicon substrate 1 and a polysilicon film 4 is formed on the gate insulating film 3.
Next, a resist (not shown) is provided on the polysilicon film 4 at a step shown in FIG. 43. The resist is then subjected to patterning by photolithography so that a resist mask is formed. Thereafter, the polysilicon film 4 is subjected to the patterning by using the resist mask. Thus, gate electrodes 41 and 42 are formed on the NMOS region NR and the PMOS region PR, respectively.
At a step shown in FIG. 44, subsequently, a resist mask R1 is formed to cover the PMOS region PR by the photolithography and an N-type impurity ion is implanted into the silicon substrate 1 by using the gate electrode 41 as an implantation mask in the NMOS region NR. Consequently, a pair of extension layers 51 are formed in the surface of the silicon substrate 1. The extension layers 51 are provided opposite to each other to interpose a region of the silicon substrate 1 provided under the gate electrode 41 therebetween. The region of the silicon substrate 1 provided under the gate electrode 41 acts as a channel region.
The extension layer is an impurity introducing layer formed to have a shallower junction than that of a main source-drain layer to be formed later, has the same conductivity type as that of the main source-drain layer, and functions as a source-drain layer. Therefore, the extension layer should be referred to as a source-drain extension layer but it will be referred to as an extension layer for convenience.
After the resist mask R1 is removed, a resist mask R2 is formed to cover the NMOS region NR by the photolithography and a P-type impurity ion is implanted into the silicon substrate 1 by using the gate electrode 42 as an implantation mask in the PMOS region PR so that a pair of extension layers 52 are formed in the surface of the silicon substrate 1 at a step shown in FIG. 45. The extension layers 52 are provided opposite to each other to interpose a region of the silicon substrate 1 provided under the gate electrode 42 therebetween. The region of the silicon substrate 1 provided under the gate electrode 42 acts as a channel region.
After the resist mask R2 is removed, a silicon oxide film (not shown) is formed to cover the whole surface of the silicon substrate 1 and is then removed by anisotropic etching together with the gate insulating film 3 provided over the silicon substrate 1 on the outside of side surfaces of the gate electrodes 41 and 42 such that it remains in only side wall portions of the gate electrodes 41 and 42 at a step shown in FIG. 46. Thus, a side wall protective film (side wall insulating film) 6 is formed.
The side wall protective film 6 is also formed on the gate insulating film 3 provided over the silicon substrate 1 on the outside of the side surfaces of the gate electrodes 41 and 42, and the gate insulating film 3 and the side wall protective film 6 form a two-layered structure. For simplicity, the side wall protective film 6 having a single layer is shown in and after FIG. 46.
At a step shown in FIG. 47, next, a resist mask R3 is formed to cover the PMOS region PR by the photolithography and an N-type impurity ion is implanted into the silicon substrate 1 by using the gate electrode 41 and the side wall protective film 6 as implantation masks in the NMOS region NR. Thus, a pair of source-drain layers 71 are formed in the surface of the silicon substrate 1.
After the resist mask R3 is removed, a resist mask R4 is formed to cover the NMOS region NR by the photolithography and a P-type impurity ion is implanted into the silicon substrate 1 by using the gate electrode 42 and the side wall protective film 6 as implantation masks in the PMOS region PR at a step shown in FIG. 48. Consequently, a pair of source-drain layers 72 are formed in the surface of the silicon substrate 1.
At a step shown in FIG. 49, subsequently, a refractory metal film such as tungsten, cobalt or titanium is formed to cover the whole surface of the silicon substrate 1 and is changed into a silicide by a high temperature treatment. Thus, a silicide film 10 is formed in portions where exposed surfaces of the silicon substrate 1 and the gate electrodes 41 and 42 are provided in contact with the refractory metal film. Then, the refractory metal film which has not been changed into the silicide is removed. Thus, a CMOS transistor 90 shown in FIG. 49 is obtained.
As described above, in the conventional manufacturing method, the extension layer 51 in the NMOS region NR is etched twice at the steps of removing the resist masks R1 and R2 and the gate insulating film 3 cannot prevent the etching of the extension layer 51. At the steps of removing the resist masks R3 and R4, the source-drain layer 71 is subjected to the etching in place of the extension layer 51.
As described above, the extension layer is formed more shallowly than the main source-drain layer. Therefore, the extension layer is affected more remarkably by the etching of the silicon substrate 1 than the main source-drain layer. In addition, the NMOS transistor has a lower channel resistance and is more affected by an increase in a resistance of a diffusion layer to be the parasitic resistance than the PMOS transistor due to a difference in a mobility of a carrier to be used.
In the conventional method of manufacturing a semiconductor device, thus, the influence of the etching of the semiconductor substrate on the NMOS transistor has not been considered. Therefore, there has been a problem in that a current driving capability is deteriorated with an increase in a parasitic resistance, and furthermore, an operating speed of a semiconductor integrated circuit is reduced.
A first aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) defining a first NMOS region and a first PMOS region for forming at least a first NMOS transistor and a first PMOS transistor in a surface of a semiconductor substrate, (b) forming a first gate insulating film on at least the first NMOS region and the first PMOS region, (c) forming first and second gate electrodes on the first gate insulating film provided over the first NMOS region and the first PMOS region, (d) covering the first PMOS region with a first resist mask and implanting an N-type impurity ion by using the first gate electrode as an implantation mask, thereby forming a pair of N-type extension layers in the surface of the semiconductor substrate on an outside of a side surface of the first gate electrode, (e) removing the first resist mask and then forming a protective insulating film over a whole surface of the semiconductor substrate, and (f) covering the first NMOS region with a second resist mask and implanting a P-type impurity ion from above the protective insulating film by using the second gate electrode as an implantation mask, thereby forming a pair of P-type extension layers in the surface of the semiconductor substrate on an outside of a side surface of the second gate electrode.
A second aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (d) includes the step of forming the N-type extension layers to have a smaller depth than 0.1 xcexcm, to have a maximum impurity concentration in the vicinity of the surface of the semiconductor substrate and to have the maximum impurity concentration set to 1xc3x971019/cm3 to 1xc3x971021/cm3.
A third aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) defining a first NMOS region and a first PMOS region for forming at least a first NMOS transistor and a first PMOS transistor in a surface of a semiconductor substrate, (b) forming a first gate insulating film on at least the first NMOS region and the first PMOS region, (c) forming first and second gate electrodes on the first gate insulating film provided over the first NMOS region and the first PMOS region, (d) covering the first NMOS region with a first resist mask and implanting a P-type impurity ion by using the second gate electrode as an implantation mask, thereby forming a pair of P-type extension layers in the surface of the semiconductor substrate on an outside of a side surface of the second gate electrode, and (e) removing the first resist mask and then covering the PMOS region with a second resist mask and implanting an N-type impurity ion by using the first gate electrode as an implantation mask, thereby forming a pair of N-type extension layers in the surface of the semiconductor substrate on an outside of a side surface of the first gate electrode, the step (e) including the step of forming the N-type extension layers to have a smaller depth than 0.1 xcexcm, to have a maximum impurity concentration in the vicinity of the surface of the semiconductor substrate and to have the maximum impurity concentration set to 1xc3x971019/cm3 to 1xc3x971021/cm3.
A fourth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (a) includes the step of defining a second NMOS region for forming a second NMOS transistor having a higher operating voltage than that of the first NMOS transistor and a second PMOS region for forming a second PMOS transistor having a higher operating voltage than that of the first PMOS transistor, and the step (b) includes the step of forming a second gate insulating film having a greater thickness than that of the first gate insulating film over the second NMOS region and the second PMOS region, the method further comprising the step of forming a pair of N-type impurity layers of the second NMOS transistor and a pair of P-type impurity layers of the second PMOS transistor in surfaces of the second NMOS region and the second PMOS region between the steps (b) and (c).
A fifth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (e) includes the step of forming the protective insulating film in a thickness of 1 nm to 20 nm.
A sixth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (e) includes the step of forming the protective insulating film as a silicon oxide film by a CVD method.
A seventh aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (e) includes the step of forming the protective insulating film as a silicon oxide film by a thermal oxidizing method.
An eighth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (e) includes the step of forming the protective insulating film as a silicon nitride film by a CVD method.
A ninth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (e) includes the step of forming the protective insulating film as a silicon nitride film by a thermal nitriding method.
According to the first aspect of the present invention, a pair of N-type extension layers are formed in the first NMOS region, the protective insulating film is then formed over the whole surface of the semiconductor substrate, and a pair of P-type extension layers are thereafter formed in the first PMOS region. Therefore, the N-type extension layer is subjected to the etching when the first resist mask is to be removed, and is then protected by the protective insulating film. Therefore, an etching amount is reduced. As a result, a junction depth of the N-type extension layer is reduced. Consequently, it is possible to obtain a semiconductor device in which a resistance value, that is, a parasitic resistance value can be prevented from being increased, a current driving capability can be prevented from being deteriorated and an operating speed can be prevented from being reduced. Moreover, arsenic or phosphorus to be the N-type impurity has a smaller diffusion coefficient than that of boron to be the P-type impurity. Therefore, in the case in which the N-type extension layer is to be formed after the formation of the P-type extension layer, the P-type extension layer is affected. Therefore, a heat treatment for activating the N-type extension layer is not fully carried out. In the present invention, however, the P-type extension layer is formed after the formation of the N-type extension layer. Consequently, the heat treatment for activating the N-type extension layer can be carried out sufficiently. Thus, it is possible to reliably recover the damage of the substrate caused by the ion implantation and carry out the diffusion of the impurity.
According to the second aspect of the present invention, the depths of the N-type and P-type extension layers are smaller than 0.1 xcexcm, and the maximum impurity concentration is obtained in the vicinity of the surface of the semiconductor substrate and is set to 1xc3x971019/cm3 to 1xc3x971021/cm3. Consequently, it is possible to obtain an extension layer which has a small resistance value and is effective in suppressing a short channel effect.
According to the third aspect of the present invention, a pair of N-type extension layers are formed after a pair of P-type extension layers are formed. Therefore, the N-type extension layer is not subjected to the etching when the first resist mask is to be removed. Consequently, an etching amount is reduced. As a result, a junction depth of the N-type extension layer is reduced. Thus, it is possible to obtain a semiconductor device in which a resistance value, that is, a parasitic resistance value can be prevented from being increased, a current driving capability can be prevented from being deteriorated and an operating speed can be prevented from being reduced. Moreover, the depths of the N-type extension layers are smaller than 0.1 xcexcm, and the maximum impurity concentration is obtained in the vicinity of the surface of the semiconductor substrate and is set to 1xc3x971019/cm3 to 1xc3x971021/cm3. Consequently, it is possible to obtain an extension layer which has a small resistance value and is effective in suppressing a short channel effect.
According to the fourth aspect of the present invention, the method of manufacturing a semiconductor device further comprises the step of forming a pair of N-type impurity layers and a pair of P-type impurity layers in the surfaces of the second NMOS region for forming the second NMOS transistor and the second PMOS region for forming the second PMOS transistor when further forming the second NMOS transistor and the second PMOS transistor which have high operating voltages. Therefore, a frequency at which the semiconductor substrate is subjected to the etching is increased. However, the N-type extension layer included in the first NMOS transistor is subjected to the etching only when the first resist mask is to be removed. Consequently, an etching amount is reduced. As a result, in a semiconductor device comprising CMOS transistors having different supply voltages, for example, a junction depth of the N-type extension layer in the first NMOS transistor having a low voltage is reduced. Thus, it is possible to obtain a semiconductor device in which a resistance value, that is, a parasitic resistance value can be prevented from being increased, a current driving capability can be prevented from being deteriorated and an operating speed can be prevented from being reduced.
According to the fifth aspect of the present invention, the protective insulating film is formed in a thickness of 1 nm to 20 nm. Therefore, also in the case in which the protective insulating film partially remains, the influence on a device characteristic can be relieved.
According to the sixth aspect of the present invention, the protective insulating film is formed as the silicon oxide film by the CVD method. Therefore, it is possible to obtain a protective insulating film having a great step coverage.
According to the seventh aspect of the present invention, the protective insulating film is formed as the silicon oxide film by the thermal oxidizing method. Therefore, it is possible to easily control a film thickness and to reduce a variation in a device characteristic which is caused by a variation in the film thickness.
According to the eighth aspect of the present invention, the protective insulating film is formed as the silicon nitride film by the CVD method. Therefore, it is possible to obtain a protective insulating film having a great step coverage. In addition, the silicon nitride film is etched by aqueous ammonia peroxide with difficulty. Therefore, the thickness can be more reduced than that in the case in which the silicon oxide film is used and the influence on a device characteristic can be relieved.
According to the ninth aspect of the present invention, the protective insulating film is formed as the silicon nitride film by the thermal nitriding method. Therefore, it is possible to easily control a film thickness and to reduce a variation in a device characteristic which is caused by a variation in the film thickness.
In order to solve the above-mentioned problems, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can prevent an increase in a parasitic resistance to inhibit a current driving capability from being deteriorated and an operating speed of a semiconductor integrated circuit from being reduced in consideration of the influence of etching of a semiconductor substrate on an NMOS transistor.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.